Numerical control system and method

ABSTRACT

A control system having a stored program digital computer for transmitting commands to digital servos for a punch press with digital to analog converter circuitry providing for a digitally selected null zone, digital control of the slope of the analog error vs. count function for optimum slow down, and digital sensing of the null condition.

United States Patent [111 3,596,266

M2 Inventors Kenneth Leonard Slnwsun [56] Relerences Cited DepeW; UNITED STATES PATENTS 3,099,777 7Il963 Davis 7 235/92 x 11H A I N 3,l83,42l S/l965 Herchenroeder 235 92 X PP 3.414.718 l2 l968 M El i 35 92 n; Filed July 12,1968 my 2 [45] Patented July 27, 19'" Primary bummer-Maynard R Wilbur [73] Assignee Houdlille Industries, Inc. Assistant Examiner-Gary R. Edwards Bull-lo, N.Y. Attorney-Hill, Sherman, Meroni. Gross and Simpson [54] NUMERICAL CONTROL SYSTEM AND METHOD 9 Davina ABSTRACT: A control system having a stored program digital [52] U.S.Cl. H 7. 340/347, computer for transmitting commands to digital servos for a 235/l5 I l l, 318/574 punch press with digital to analog converter circuitry provid- |5 l| lnt.Cl. i "03k [3/02 ing for a digitally selected null zone, digital control of the (50] Field 0! Search 340/347; slope of the analog error vs. count function for optimum slow 235/ l 54. 92, 3 1 8/28 down, and digital sensing of the null condition.

l Pr:

CGNVIRVER Clea/Ir mmm PATENTFUJULZTISTI iLSSbZbEj sum 1 OF 7 ROB J- KE HER ATTOR EYS KENNETH L. SLAWSON PAIENIED JUL 2 7 19m SHEET 5 UF 7 NUMERICAL CONTROL SYSTEM AND METHOD CROSS-REFERENCES TO RELATED APPLICATIONS The present application discloses specific improvements on the subject matter of copcnding application of Kenneth Leonard Slawson, U S. Ser. No. 652.968 filed July 12, 1967, now abandoned which is assigned to the assignee of the present application, and the disclosure of said copending application is incorporated herein by reference. The present application relates to a commercial numerical control system which is disclosed in greater detail in a further commonly assigned application of Kenneth Leonard Slawson US. Ser. No. 744,392 filed July 12, I968. and the disclosure of said further application is also incorporated herein by reference.

SUMMARY OF THE INVENTION A basic objective of the present invention is to provide a substantially more reliable machine tool control system.

Another object of the invention is to provide a machine tool control system which is capable of convenient adjustment to respond to a desired digital null one.

A further object resides in the provision of a control system having a digitally responsive slow down characteristic which can be tailored for optimum positioning efficiency under different operating conditions.

BRIEF DESCRIPTION OF THE DRAWINGS FIGS. 1A and 1B show the X-axis control circuits of a numerical positioning control system in accordance with the present invention, FIG. 18 being a continuation of FIG. 1A to the right, and dash lines being utilized to represent stages which have been omitted;

FIG. 2 is a diagrammatic illustration showing means for controlling the transfer of digital command signals from a stored program digital computer to the X and Y control circuits of a plurality of machine tools;

FIG. 3 is a diagrammatic illustration similar to FIG. 2 but showing the means for transferring data from the control circuits of the machines to the computer;

FIG. 4 is a logic diagram illustrating a portion of the con verter circuitry for a system in accordance with the present invention;

FIG. 5 is a diagrammatic illustration of a further portion of the converter circuitry having extensive interconnections with FIG. 4;

FIG. 6 illustrates diagrammatically servocontrol circuitry which is connected with the circuitry of FIG. 4;

FIG. 7 is a diagrammatic illustration of servo circuits for the system; and

FIG. 8 is a diagrammatic showing of the control circuit for the MOVE flip-flop in the system.

DESCRIPTION OF THE ILLUSTRATED EMBODIMENT By way of introduction of the illustrated circuitry the components shown in FIGS. l8 of the drawings have been assigned respective general reference numerals, and a brief description of each such component is given in the following tabulations. The components of each figure have in general been assigned three or four digit reference numerals wherein hundreds digit of the reference numeral corresponds to the figure number, (the reference numerals in FIGS. 1A and 18 beginning at 100, those in FIG. 2 beginning with 200 and so forth) except that the same component appearing in successive drawing figures has received the same reference numeral. The tabulations also refer to a suitable commercial source where the component is commercially available, or otherwise identify or explain the structure of the component.

TABLES (IF EXEMPLARY COMPONENTS IAIiLE I (FIGS. IA AND 18) idvntilylng component Description of compollt'ill Binary i'p-Down Counter.

(See DEC A, 2 pages 39 and 40. which is incorporated herein by R201 (17 required).

reference). Read XL Selector W103.

(code 6744). 101 Load XL Selector W103.

(code 6724). 102 Clear XL Selector W103 (code 6722) 103 Pulse Amplifier... R002. 04. XL Read Uut Gates R123 2| tillllvtl 105. Digital-Analog Con- Figs. 4-6.

verter circuitry. 108. XL Road Out Oates R123. X-Axis Servo Circuits Figs 7 111 X-Axis Servo Drive. l'ait oi pivsvut numericaily controlled positioning systems. 112 X-Axls Feedback Do.

Transducer. 113 Read XU Selector W103.

(code 6731). 114.... Load XU Selector W103.

(code 0734). 115. Hold X Selector W103 (code 6741). 116 Clear X U Selector W103 (code 6732). 117. Synchronizer (X-Axis Seithe fourth Figure 01' the referenced Slawson applications 118 Pulse Ampliflen. R602.

TABLE II (FIGURE 2) Component Identification of rel 0. Component description uitable source 200.. Computer Data Output Circuits Part of PD? nus.

(See DEC-B. which is incorporated herein by reference.) 501.. Output Bus Drivers. Do. 202. IOP (In ut-Output Pulse) Pulse Do.

Genera or. 203. X-Axis Lower Read-in Gates Part of R201 \I! required! 204 X-Axis Upper Read-in Gates. Part of R201 (5 required) 205. Y-Axis Lower Read-In Gates. Part 01' R201 112 re uired) 206. Y-Axis Upper Read-In Gates. Part of R201 (3 reqnirvd) 2012.. Load YL Selector (Code 6754).... W103 208 Load YU Selector (Code 6764). W103.

l Avaiilable from Digital Equipment Corporation unles othwwise specific 1 DEC-B refers to The Digital Small Computer Handbook published by Digital Equipment Corporation. 1967 Edition (494 pages).

TABLE III (FIGURE 3) 1 DEC is used herein to refer to the Digital Equipment orporation, aynard, Massachusetts. USA.

TABLE IV (FIGURE 4) DEC module Conlrponent desigref. 0. Component description nat on 1401,1401. NAND Gates R113 1403. 1404. Diode Networks R002 ompuneni desigrcf \u (omponenl dettnpnon nation 1405,1415 NAN!) H1110 R111 140? ii'oluluctors lrnm H05 and H06 connected (l1- rectiy to input of 1415 1411 1414 DlDdt Networks R002 1415,1515. NAN!) Hales R111 1417 (Outputs 011415 and ltlficonnected to input 01 14m 1418. inverters R111 1421 1423. Diode Networks R002 1424,1425 NAXI) Gales R111 142a. (Outputs 1425 and 1425 connected directly to the input of 1427) 1427. inverter R111 1431. Diode Network 7 R002 1432-1434 NAND Gates R111 1435,1136. inverters R107 TABLE (FIG.

DEC module Corn nent dcsigref. 0. Component description nation 1511. 1502. Converter Stages A001 1503-1511 Resistance values of 1,111) ohms, 7,000 ohms,

8,000 ohms. (.000 ohms, 2.111] ohms. 7,000 ohms, 8,000 ohms, 4,01!) ohms, and 2,000 ohms, respectively.

1512-1517 1.. Amplifiers 1521. Resistance value of 100 ohms. two watts.

1522. Zener Diodc1N3732..

1531.. X gaitr potentiometer, 0 to 1,000 ohms, two

1532.. Resistance value 31!] ohms, one hall watt.

1533.. Resistance value 1,000 ohms, one half watt.

1531. X Zgro potentiometer, 0 to 500 ohms, two

wa ts. 1535 Resistance value 1,800 ohms, one hall watt. 1511-1546. A direct conductive connection is utilized to [20311 the logica] 0R" function as in 15514562..." NAND Gates R111 TABLE \'1 (FIGURE 0) DEC module Com nent desigrcl. 0. Component description nation Will-1W Diode Networks R002 1604-1007 NAND Gates... R111 1611,1612. Diode Networks R002 1620. Relay Circuit. W800 1621,1622. NAND Gates.

1623, 1624. Relay Energizing Coils.

1625, 1626. Normally open contacts 01 r lays i023 and 1624 respectively.

1631. Resistance value 1.500 ohms. one hall watt.

1032. X balance potentiometer. zero to 1.000 ohrns,

two watts.

I633. X rapid potentiometer. zero to 10.000 ohlns.

two wattsv 1611-1644. Switch Filters... W700 1051 1651. inverters R10? 1661, 1662 Diode Networks R1112 0363,1064. NOR Gates R111 1670. Relay. W800 1671, 1672... NAND Gates 1675, 1676. Normally open contacts or |cla 1673 and 1674,

respectively.

TABLE V11 (FIGURE 7) DEC module Component desig- Rel. No. Component description nation 1,700 Transformer with 117 volt alternating current primary, 2.3 kilovolt ampere.

1701, 1702 Conductors connected to terminals 01 secondary winding 0! 1700 with a filter connected across the secondary winding between 1701 and 1702.

1708, 1701"-.. Conductors connected to opposite terminals 0! a secondary winding with filter thereacross.

1705, 1706. Conductors connected to opposite terminals 01' a lull wave rectifier energized by a secondary winding of the transformer of 1700 so that conductor 1706 is 01 negative polarlty.

1711,1712 Servo preampliflers A-110973' 1721, 1722. X and Y tachometers 1723 Balance switch lABLl' \ll lFlGURE l-('onnnued DEl module Component desig- Ref. No Component description nation R2, R11. Resistance values 2.000 ohms each.

two watts. R4, R10. Resistance values 4,000 ohms each.

five watts. R3, R0 Potentiometer, zero to 2,500 ohms,

ten watts.

10 L1, L2... inductance values, 1.5 henr'les each...

R5, 23,1 18, R24. Resistance values 1,500 ohms each,

two watts. R6, R7. Resistance values 3 ohms each, 100

watts. CR-3, (IR-l, CR- Controlled rectifiers 251686 5 and C R-6. l5 1731, 1782. X and Y armatures 1733, 1734.. X and Y fields.

Supplied by Hughes Aircraft Company.

TABLE \111 (FIGURE 8) Component DEC module Ref. No. Component description designation 1801. M OVE Flip-Flop. R203 180': NAND Gate R111 1803... DiodeNetworlr... R002 1804... Diode Network.. R001 1805 Clamped Load W005 1811.... Pulse Am lifier. new 1812.... Clamped oad W005 1813.. Delay (One Shot) (C9=38 microiarad) R302 Operation of P168. 1A and 1B In operation of the components of FIGS. 1A and 18, digital command signals from the accumulator (AC) of the computer are supplied via bus cable 130. As indicated by reference characters applied to conductors branching from the cable 130, the input gates of counter stages XL" and XU11 are connected with the BACll output from component 201, FIG. 2, of the computer output circuits 200, which thus constitutes a source of digital command signals. The read in gates for stages XLll through XLO are represented by block 203 in FIG. 2, and the read in gates for stages XU11, XU10, XU9, XU8 and XUO are represented by component 204 in F10. 2. The BAC 10 terminal of the computer is connected with stages XL") and XU11), the terminal BAC9 is connected with XL9 and XU9, and the terminal BAC8 is connected with XLB and XU8. The terminals BAC7 through BACi are connected with countcrstagcs XL7, XL6, XLS, X114, XLS, XLZ and XLl, respectively. The BACO terminal of the computer is conncctcd with the input gate of counterstage XL!) and also with the input gate of counterstage XUO, both shown in FIG. 1.

Thus, when the load XL component 101 is selected by virtue of the output of component 201, HO. 2, the gates 203, FIG 2, will be enabled to load digital command signals from the computer into the XL counting stages. Similarly when the load XU component 114 is selected, digital command data will be loaded into the XU counting stages of FIG. 1B.

When a positioning cycle is then initiated, an analog error signal will be generated at the output 1538 of the digital to analog converter circuitry 105 which will determine the direction and speed of operation of the X-axis servodrive 11. As shown in FIG. 1A, the complement outputs of stages XL1l-XL6 are supplied via lines 141-146. These lines are connected to the inputs of the converter circuitry 105. The circuitry specifically referred to in Table 1 is such that when XL" is clear, conductor [41 is held at minus 3 volts. 0n the other hand, when the counting stage XL] 1 is set, the output at line 141 is at ground potential.

Rccauae ofthc operation of the null detector in circuitry 105 it is possible for the machine axis to come to a stop with a count other than were registered in the counting stages. The count remaining in the counting stages may be determined so as to be well within the tolerance requirements of the machine tool, and yet with many successive positioning steps, it is condeal with this possibility. provision is made for the computer to read the condition of the counting stages when the axis has stopped. The computer could be programmed in a number of different ways to take care of the problem, but in the illustrated embodiment, pfOHSIOI't is made for the computer processor to algebraically combine the remainder in the counting stages with a succeeding command so as to provide a modified command signal for the control circuits which will correct for the error in the previous positioning operation.

For the purpose of detemiining the condition of the count ing stages afler the machine axis has stopped, the counting stages are provided with output lines such as those indicated at 186-195 leading from the set output lines of stages XLlI XLS, XLO, XUI I, XUB and XUO. Similar output lines would provided for stages XL4, XL3, XLZ, XLI, XUIO and XU9. The XL output lines such as 185- I92 lead to an XL Read Out Gates component I04 controlled by a Read XL component I00. The XU Read Out Gates component I03 receives the output lines such as I93I95 of the XU counting stages and is controlled by the Read XU component 113. As indicated by the reference characters applied to the output lines of the XL Read Out Gates component I04, cable 197 connects with terminals ACII through ACO of the computer accumulator. Similarly the output lines from the XU Read Out Gates component 108, FIG. 18, lead to terminals AC1], ACIO, AC9, AC8 and ACO, respectively. The gate components I04 and 103 are of course, enabled on different cycles so that the computer can distinguish the ACH output of gate 104 from ACIl output of gate I08, for example.

In the foregoing description, certain output lines which connect with the same terminal of the computer have been identified with a reference character indicating this fact. Specifically the designations ACO through AC 11, and BACO through BA II have this significance. Individual reference numerals have also been applied to the respective conductors bearing the more general reference character designations. [t is believed that this procedure will facilitate comprehension of the drawings by those skilled in the art Similarly in the following description the outputs from the XL and XU counting stages have been designated by the same reference characters as used for the respective counting stages. Thus, in FIG. IA, an output line from the "set" output terminal of counterstage XLS has been designated by the reference character XLS, while the output from the "clear" terminal of counting stage XLS has been designated with the symbol for the complement of XLS (XLS). (Referring to FIG 1A, it will be observed that line 191 is connected to a common circuit point with line XLS at the "set" output of counting stage XLS.)

Referring to the lower part of FIG. 1B, the output line 174 from servo circuits 110 is connected to the input of the X-axis servodrive component Ill whose mechanical output is indicated by dash line 198. The transducer component 112 may be of the photoelectric type and include a suitable preamplifier so as to supply square waveform signals at the output lines MIX and MZX leading to synchronizer 117. The synchronizer component will enable the line designated as the complement of XM (iv) if the transducer is rotating in one direction n d will enable the line designated as the complement of XP (XP) if the transducer is being driven in the opposite direction. The synchronizer 117 will also supply an X clock pulse or motion pulse at line 199 for each increment of rotation of the transducer I12 By way of example, the transducer may be mechanically coupled to the output shaft I98 in such a way as to produce an X clock pulse for each increment of rotation corresponding to a linear displacement of the machine axis of 0.001 inch. The X clock pulses from the synchronizer are supplied to the input of counting stage XLII which is arranged so that each clock pulse causes the counting stage to change its state. The stage XLll thus acts in the m ner of a toggle switch or binary counting stage. If the line XM is enabled, the counting stages will count in the up" or positive direction. On the other hand if the linefi is enabled, the "set" output of each counting stage is efi'ectively coupled to the next succeeding counting stage so that the counting stages will count in the "down" or minus direction The Hold X component I15 causes synchronizer II? to interrupt the supply of X clock pulses for a sufficient interval to ensure that the counting stages may be inspected by the computer The "hold" interval introduced by actuation of component [I5 is sufficiently short, however. so that any feedback pulse from transducer 112 which might occur during this in' terval could only be blocked for a portion of its duration Thus even ifa slight movement of the feedback transducer occurred during the hold interval, the count in the counting stages would reflect such movement. (Further details of the Hold X operation will be apparent from the referenced Slawson applications.

Afler the computer has read out the condition of the counting stages with the machine axis essentially stopped, the computer will actuate Clear XL component 102 and the Clear XU component 116 to reset the counter to a zero reading in preparation for the transfer of a new digital command signal. Of course, if the read out from the counter shows an error in excess of tolerance. the computer may be programmed to delay clearing the counter, and to enable the servo drives for an additional interval.

Operation of FIGS. 3 and 3 In FIG. 2, the BAC output bus I30 has been indicated as leading to input conductors 22I-232 of gate component 203. These same reference numerals have been applied in FIG. 1A and FIG. 18 to assist in correlation of these figures. Input conductors 221 227 as shown in FIG. 1A are also designated by reference characters BACII through BACS to indicate that these conductors are connected by means of cable with terminals BACII through BACS of component 201, FIG. 2. Similarly, conductor 232 in FIG. 18 has also been designated by the reference character BACO which is the terminal to which this conductor connects at component 20! The input conductors to gate component 204 in FIG. 2 have been designated by reference numerals 24I245 and lead. respectively, to terminals BACI I, BACIO, BAC9, BACS and BACO In practice, the cable I30 may lead to a connector at the com' ponent 203, and a fu ther cable such as indicated at 1300 may lead from component 203 to component 204, while cable l30b may lead from component 204 to component 205, cable I30: may lead from component 205 to 206, and cable I30 d may lead to a further component ofa second machine tool, for example. By actuating components 203, 204, 205, 206 and subsequent corresponding components in sequence, a desired number of components may all connect with terminals BACI I through BACI] of component 20!. Thus, conductors 251 262 of gate 205 would connect with terminals BACII through BACO of component 201 and conductors 271 273 of component 206 would connect with terminals BACII, BACIO and BACO of component MI.

The manner of selection of gates such as 203- 206 in sequence is explained in detail in The Digital Small Computer Handbook (cited in Table II. supra) at pages 429 and 430, and a specific circuit is disclosed for components 10], I14, 207, and 208 in The Digital Logic Handbook (cited in Table l. supra) at page 142, and these disclosures are incorporated herein by reference. In general, the BMB cable 280 from component 201 (or two multiconductor cables as represented by line 280) may contain at least l2 conductors. Lines 281 284 may represent connections from one of each of six pairs of conductors of cable 280 to components 101, 114, 207 and 208, for example. The memory buffer register of the computer may have bits 3-8 thereof connected at both the binary l and binary 0 outputs thereof to the component 201, and cable 280 may connect with terminals MB3(I) through MBSH) and MB3(0) through MB8(0) of component 201. The corresponding outputs of component 201 would be BMB3(I) through BMB8(1) and BMB3(0) through BMB8(0). It may be noted that the convention used for the selectors herein is to use the middle two digits of the code numbers of the selectors to indicate the octal complement of the BMB selection pattern. The final digit indicates whether an IOTl. [T2 or [0T4 pulse is supplied. The initial 6 in the code indicates an input/output selection signal. Thus the selector I0l with a code of 6724 would be addressed on BMB cable 280 by a selection code of 72 (octall, with the final digit 4. indicating that an [0T4 is to be transmitted. Thus. taking the selection code for component I01 as 72 (Octal), the following terminals would be connected to component 10] via cable 281 BMB3(0l. BMB4(0), BMB5(0) and BMBGH). BMB7(0). BMB8(Ii To give one further example, if the code for component I14 is 73 (octall. then cable 282 would connect with the following terminals: BMB3t0), BMB4(0). BMB5(0) and BMB6(1), BMB7(0), BMB8(0). It is evident that any number of additional device selectors may be assigned two digit octal codes (up to a total of 63 in decimal notation). The operation of each of the selector components such as 101, I14. 207, 208 in FIG. 2 and such as 100, I13. 302 and 303 in FIG 3 will be apparent from the foregoing description.

In FIG. 2. branch cables as indicated at 285-288 leading from IOP cable 290 to selectors I01, I14, 207 and 208, respectively. The cable 290 is connected to the output of an IOP bus generator component 291 of the computer, and the cable 290 may comprise three conductors carrying respective pulses IOPI IOP2. and IOP4 as described, for example, in The Digital Small Computer Handbook. supra, at pages 88-90. pages 22l-223, and pages 426-427. and this description is incorporated herein by reference. The device selector components when enabled regenerate the respective IOP pulses as IOT command pulses. The positive or negative version of any of the successive regenerated pulses IOTI, |OT2 or IOT4 may be supplied via output lines such as indicated at 291-294 in FIG. 2. The output terminals in FIG. 2 to which conductors 291-294 are connected are designated by letters which correspond to the distinctive letters in the terminal designations utilized in the commercially available module W103. Thus, terminal S of selector 101 may supply an initially positivegoing version of the 10T4 pulse, the T terminal of selector 100 may supply an initially negative-going IOT4 pulse. for example. and the terminal F of selector 113 may supply an initially negative-going 10Tl pulse. The timing of the WT cycle is shown at page 425 of The Digital Small Computer Handbook. supra, and this disclosure is incorporated herein by reference.

In FIG. 3, the reference numeral 197 designates generally the cable extending between the accumulator terminals AC 11 through ACO of the computer and the successive gate components such as 104, 108. 300 and 301 As mentioned with reference to cable 130, the cable 197 may actually comprise successive lengths of multiconductor cable. for example connecting from component 30] to the computer, connecting between components 300 and 301. connecting between components 108 and 300, and connecting between components 104 and 108. Further lengths of cable may connect gate component 104 with gate components for other axes or for the axes of other machines, or separate bufi'enng may be utilized in conjunction with a separate cable directly from the computer as will be apparent to those skilled in the art.

In FIG. 3 the conductors leading from components 104. 108, 300 and 30] have been assigned reference numerals 321-332. 341-345, 351-362 and 371-373. The reference numerals 321-327, 332 and 341. 344 and 345 have been applied to the corresponding conductors in FIGS. 1A and 1B. Conductors 321-332 connect with terminals AC1! through ACO of the computer, conductors 341-344 connect with ter minals ACll through AC8, conductor 345 connects with terminal ACO, conductors 351 through 362 connect with terminals ACll through ACO, conductors 37l and 372 connect with terminals AC" and AC10. and conductor 373 connects with terminal ACO.

The structure and function of conductor cables 385388 and conductors 39l-394 in FIG. 3 will be apparent from the comparable discussion with respect to cables 285-288 and conductors 29] 294 of FIG 2 Operation of FIGS 4-8 FIGS. 4-8 illustrate improvements which have been made in the production of a commercial system now in successful operation In FIG 4. conventional logic symbols have been utilized so that the operation of the circuit will be apparent to those skilled in the art. The inputs to the various gate circuits have been labeled in conformity with the designations of the out puts from the counting stages of FIGS IA and IB Thus, when the counterstage XLll is in a ONE indicating condition. an output voltage of minus 3 volts appears at the 1" output ter minal so that the output XL" is TRUE." and the 0" output XLII is FALSE." Conversely, when the counterstage XL" is in the ZERO representing condition. the output terminal XI 11 will be at minus 3 volts. and the 1" output XLll will be at ground potential.

The Tables A1 and A2 on the following pages will illustrate respectively the count values at which the various outputs in FIG. 4 will assume their "TRUE" condition. and the analog outputs from FIG. 5 as a function of different count values.

TABLE AI-CRITICAL COUNT RANGES IN FIG. 4

Converter Control Output (FIG 4) Range of Counts For which Output is "TRUE" (-3 Volts] (Positive Cou nts] TABLE A2. ANALOG OUTPUT IN FIGURE 5 (IN ARBI- TRARY UNITS) AS A FUNCTION OF CU U'NT Input to converter unit (N 3 Analog volts) (G=ground) output (ount range I 2 4 S 16 32 Total Net 384 to 65536 N N N N N G 32 i 64 to 384 G G G G G G 63 3t 48 to 62. G G N G G G 59 27 40 to 47 G G G N G G 55 23 32 to 39 G G N N G G bl 19 24 to 31. G G G G N G 47 15 16 to 23. G G N G N G 43 H 8 to 15. G G G N N G 39 I 3 to 7.. G G N N N G 35 3 2 N G N N N G 34 2 l. G N N N N G 33 l 0. N N N N N G 32 l) l G G G G G N 31 -l 2 N G G G G N 30 -2 3 G N G G G N 29 3 4 to B N N G G G N 28 4 9 to 16 N N N G G N 24 B -17 to 24. N N G N G N 20 -12 25 to 32 N N N N G N 16 -18 33 to -40. N N G G N N 12 -20 41 to 48- N N N G N N 8 -24 49 to -64. N N G N N N 4 28 65 to 384- N N N N N N 32 385 to 65536. N N N N N G 32 0 Bias equals minus 32 units.

Interconnections between FIGS. 48

To assist in identifying the connections between FIGS. 4

and 5, reference numerals 1441-447 have beenfassigned in FIG. 4 and conductors 1441-1444, 1446 and 1447 are also indicated in FIG. 5. Conductor I441 also connects with one input of components 1601 and 1602, FIG. 6. Conductor I445 connects with an input to NOR gate 1663, FIG. 6. Conductor 1444 also connects with an input of component 1802, FIG. 8.

Conductor 1537 at the right in FIG. 5 connects with the,

movable tap of potentiometer 1633, FIG. 6. Conductor I538 at the right in FIG. 5 connects with an input to the X-axis servo preamplifier 1711, FIG. 7.

In FIG. 6 the showing of certain Y-axis components corresponding to components I60I-1607, 1611, 1612, 1620- 1626, 1631-1633 of the X-airis has been omitted since they are entirely similar to the X-axis components. As indicated at 1681, the Y-axis components would include MAN OUT and MAN IN switches similar to the MAN LEFT and MAN RIGHT switches 1682 and 1683. Conductor 1684 for the Y- axis components corres nds to conductor I685. The conductor 1686 (INHIBIT MOVE) would connect to the Y-axis diode networks corresponding to 1611 and 1612.

In FIG. 6, at high limit counts, the relay 1620 serves to supply a saturating current of proper polarity to the conductor 1537, FIG. 5, to saturate preamplifier 1711, FIG. 7, with the proper polarity to correct for the existing error.

The structure and operation of the various Y-axis circuits correspond to that explained for the X-axis.

In FIG. 8, the monostable 1813 may use a capacitor C9 of 38 microfarads. The circuit 1813 may be adjusted to provide a time delay of approximately I milliseconds, so that both the X and Y low limit inputs must be TRUE" for at least 100 milliseconds before the MOVE flip-flop 1801 is reset.

Operation of FIGS. 4-8

Alter source 200 has loaded the digital command signals into the countercircuits such as shown in FIG. 1A and 15 via cable 130, conductors 221-232, 241-245, 251-262 and 271-273 and the gates 203-206, the digital-analog circuitry such as represented at 105, FIG. 18, and as shown in detail in FIGS. 4 and 5, supplies a corresponding analog error signal to conductor 1538, FIG. 5, which is designated "To X Servo Ref." As shown in FIG. 1B, conductor I538 connects with the X-Axis Servo circuits component 110 which together with the X-Axis Servodrive component III is shown in detail in FIG. 7.

As previously stated, at high limit counts, relay 1620, FIG. 6, serves to supply saturating current of proper polarity to the conductor 1537, FIG. 5. As seen at the right in FIG. 5, conductor 1537 connects with the output conductor 1538, serving to saturate preamplifier 1711, FIG. 7, with the proper polarity to correct for the existing error.

As shown in Table A2, (the right hand column) the analog output from FIG. is reduced to a net value of plus 31 for the count range between 64 and 384, and then progressively reduces to net values of 37, 23, l9, [5, II, 7, 3, 2, l and 0 for successive count ranges down to a count value of 0. Similarly where the counts are negative, the analog output has a net value of minus 32 for counts in the range from minus 65 to minus 384, and the net analog output decreases in magnitude toward zero as the count range approaches the count of 0.

As indicated in Table Al, the converter control output Low X Limit becomes "TRUE" for the range of counts including positive count values of l, 2, and 3 immediately adjacent to the count value of 0 and including negative count values of minus I, minus 2, minus 3 and minus 4, immediately adjacent to the count value of 0, the range including the count value of 0 also. The digital null circuit for the X-axis for uniquely sensing error counts which are within the predetermined null range of count values in the vicinity 010 is shown in FIG. 4 and the output Low X Limit is designated by reference numerical 1444 at the right-hand side in FIG. 4.

The digital null circuit for each axis is responsive to error counts within the predetermined null range where Low X Limit is "TRUE" to establish a digitally determined null condition, namely the presence of a potential of minus 3 volts at conductor 1444*(see the heading for the right-hand column of table AI As shown in FIG. 8, when "X Low Limit and Y Low Limit" are both "TRUE" monostable delay component 1813 is actuated to begin its timing interval. If both X Low Limit and Y Low Limit are still TRUE at the completion of the timing interval, pulse amplifier 1811 is triggered to restore MOVE flip-flop component 1801 to the "CLEAR condition, whereupon the "MOVE" output from flip-flop 1801 becomes "FALSE" to represent a move-complete signal.

As previously explained in describing the operation of FIGS. IA and 18, because of the operation of the null detector in circuitry 105, it is possible for the machine axis counters to have a count other than 0 registered therein at the time that the move-complete signal is generated. To deal with this possibility the count in the countercircuits is read by means of gates such as 104 and 108, FIGS. 1A, 1B and 3, and gates 300 and 301, FIG. 3, which supply outputs to conductors 321-332, 341-345, 351-362 and 371-373 leading to the computer accumulator via cable 197, FIG. 3. As previously explained, provision is made for the computer processor to algebraically combine the remainder in the counting stages with a succeeding command so as to provide a modified command signal which will correct for the error in the previous positioning operation.

We claim as our invention:

1. A control system comprising:

a source for supplying digital command signals representing a movement of a load with respect to X and Y-axes to a desired end point, X and Y-axis servo drives coupled to the load and responsive to respective X and Y-axis analog error signals for driving the load as a function of said analog error signals relative to the respective axes, a transducer coupled to each of said servo drives so as to be driven thereby as the load is moved relative to the corresponding axis and for generating motion pulses as a function of the movement of the load relative to the corresponding axis, a countercircuit for each axis connected with said source for registering the digital command signal for the axis and coupled with said transducer for the axis for receiving said motion pulses and operable to maintain an error count representing the displacement error of the load relative to the desired end point with respect to the axis, digital-analog circuitry for each axis connected with the corresponding countercircuit for providing an analog error signal in accordance with the magnitude of the error count in the corresponding countercircuit and connected with the corresponding servodrive for supplying said analog signal thereto for causing said servodrive to move the load toward the desired end point with respect to the axis, and move-complete circuit for generating a move-complete signal, wherein the improvement comprises: said digital-analog circuitry including a digital null circuit for each axis connected with the countercircuit for the axis and with the move-complete circuit and operable for uniquely sensing error counts registered by the corresponding countercircuit which are within a predetermined null range of count values in the vicinity of 0 including a count value of 0 and including positive and minus count values immediately adjacent to the count value of 0, and responsive to error counts within said predetermined null range to establish a digitally determined null condition,

said move-complete circuit being responsive to the ex istence ofa null condition for each axis simultaneously for a predetermined time interval to generate said move-complete signal.

2. The control system of claim 1 wherein the digital null circuit for each axis generates a predetermined logical signal level when in said digitally determined null condition, said move-complete circuit including a bistable component which is in one stable condition during a positioning operation and which is actuatable to a second stable condition to generate said move-complete signal said move-complete circuit including a logical AND gate having inputs receiving the respective predetermined logical signal levels for the respective axes and for transmitting an output signal so long as said predetermined logical signal levels are both present, a monostable delay circuit connected to the output of the AND gate for beginning a timing cycle in response to said output signals from the AND gate, and means connected to the output of the monostable delay circuit and to the output of the AND gate and to said bistable circuit for shifting the bistable circuit to the second stable condition in response to a delayed output from the monostable delay circuit providing the output signal is still present at the output of said AND gate.

3. A control system comprising:

a source for supplying digital command signals representing a movement of a load with respect to X and Y-axes to a desired end point X and Y-axis servo drives coupled to the load and responsive to respective X and Y-axis analog error signals for driving the load as a function of said analog error signals relative to the respective axes,

a transducer coupled to each of said servo drives so as to be driven thereby as the load is moved relative to the corresponding axis and for generating motion pulses as a function of the movement of the load relative to the corresponding axis,

a countercircuit for each axis connected with said source for registering the digital command signal for the axis and coupled with said transducer for the axis for receiving said motion pulses therefrom and operable to maintain an error count representing the displacement error of the load relative to the desired end point with respect to the 12 axis,

digital-analog circuitry for each axis connected with the corresponding countercircuits for providing an analog error signal in accordance with the magnitude of the error count in the corresponding countercircuit and connected with the corresponding servodrive for supplying said analog signal thereto for causing said servodrive to move the load toward the desired end point with respect to the axis, and

a move-complete circuit for generating a move-complete signal,

said digital-analog circuitry including a digital null circuit for each axis connected with said countercircuit for the axis and directly responsive to a zero count value in digital form in said countercircuit to establish a discrete logical signal level signalling a digitally determined null condition,

said move-complete circuit including digital logic circuitry connected to the digital null circuits for the respective axes and responsive to the simultaneous existence of the digitally determined null condition for each axis to begin a timing cycle, said move-complete circuit being responsive to the simultaneous existence of said digitally determined null condition for each axis at the termination of the timing cycle to generate said move-complete signal.

4. A control system in accordance with claim 3 with said digital null circuit for each axis comprising logical AND circuitry with inputs connected to the respective stages of the countercircuit for responding to the zero count value in digital form in said countercircuit to establish said discrete logical signal level, said move-complete circuit comprising a logical AN D circ iit having inputs connected to the respective digital null circuits and a timing circuit connected with the output of the logical AND circuit for beginning a timing cycle when both inputs to said logical AND circuit are at said discrete logical signal level signalling said null condition. 

1. A control system comprising: a source for supplying digital command signals representing a movement of a load with respect to X and Y-axes to a desired end point, X and Y-axis servo drives coupled to the load and responsive to respective X and Y-axis analog error signals for driving the load as a function of said analog error signals relative to the respective axes, a transducer coupled to each of said servo drives so as to be driven thereby as the load is moved relative to the corresponding axis and for generating motion pulses as a function of the movement of the load relative to the corresponding axis, a countercircuit for each axis connected with said source for registering the digital command signal for the axis and coupled with said transducer for the axis for receiving said motion pulses and operable to maintain an error count representing the displacement error of the load relative to the desired end point with respect to the axis, digital-analog circuitry for each axis connected with the corresponding countercircuit for providing an analog error signal in accordance with the magnitude of the error count in the corresponding countercircuit and connected with the corresponding servodrive for supplying said analog signal thereto for causing said servodrive to move the load toward the desired end point with respect to the axis, and a move-complete circuit for generating a move-complete signal, wherein the improvement comprises: said digital-analog circuitry including a digital null circuit for each axis connected with the countercircuit for the axis and with the move-complete circuit and operable for uniquely sensing error counts registered by the corresponding countercircuit which are within a predetermined null range of count values in the vicinity of 0 including a count value of 0 and including positive and minus count values immediately adjacent to the count value of 0, and responsive to error counts within said predetermined null range to establish a digitally determined null condition, said move-complete circuit being responsive to the existence of a null condition for each axis simultaneously for a predetermined time interval to generate said move-complete signal.
 2. The control system of claim 1 wherein the digital null circuit for each axis generates a predetermined logical signal level when in said digitally determined null condition, said move-complete circuit including a bistable component which is in one stable condition during a positioning operation and which is actuatable to a second stable condition to generate said move-complete signal said move-complete circuit including a logical AND gate having inputs receiving the respective predetermined logical signal levels for the respective axes and for transmitting an output signal so long as said predetermined logical signal levels are both present, a monostable delay circuit connected to the output of the AND gate for beginning a timing cycle in response to said output signals from the AND gate, and means connected to the output of the monostable delay circuit and to the output of the AND gate and to said bistable circuit for shifting the bistable circuit to the second stable condition in response to a delayed output from the monostable delay circuit providing the output signal is still present at the output of said AND gate.
 3. A control system comprising: a source for supplying digitAl command signals representing a movement of a load with respect to X and Y-axes to a desired end point X and Y-axis servo drives coupled to the load and responsive to respective X and Y-axis analog error signals for driving the load as a function of said analog error signals relative to the respective axes, a transducer coupled to each of said servo drives so as to be driven thereby as the load is moved relative to the corresponding axis and for generating motion pulses as a function of the movement of the load relative to the corresponding axis, a countercircuit for each axis connected with said source for registering the digital command signal for the axis and coupled with said transducer for the axis for receiving said motion pulses therefrom and operable to maintain an error count representing the displacement error of the load relative to the desired end point with respect to the axis, digital-analog circuitry for each axis connected with the corresponding countercircuits for providing an analog error signal in accordance with the magnitude of the error count in the corresponding countercircuit and connected with the corresponding servodrive for supplying said analog signal thereto for causing said servodrive to move the load toward the desired end point with respect to the axis, and a move-complete circuit for generating a move-complete signal, said digital-analog circuitry including a digital null circuit for each axis connected with said countercircuit for the axis and directly responsive to a zero count value in digital form in said countercircuit to establish a discrete logical signal level signalling a digitally determined null condition, said move-complete circuit including digital logic circuitry connected to the digital null circuits for the respective axes and responsive to the simultaneous existence of the digitally determined null condition for each axis to begin a timing cycle, said move-complete circuit being responsive to the simultaneous existence of said digitally determined null condition for each axis at the termination of the timing cycle to generate said move-complete signal.
 4. A control system in accordance with claim 3 with said digital null circuit for each axis comprising logical AND circuitry with inputs connected to the respective stages of the countercircuit for responding to the zero count value in digital form in said countercircuit to establish said discrete logical signal level, said move-complete circuit comprising a logical AND circuit having inputs connected to the respective digital null circuits and a timing circuit connected with the output of the logical AND circuit for beginning a timing cycle when both inputs to said logical AND circuit are at said discrete logical signal level signalling said null condition. 